The present invention relates to a control method and a control apparatus suitably applicable to the constitution of a packet switched network and to a packet transfer.
The packet switching capacity of the present packet switching system is 10.sup.4 packets per second when the D51-type packet switching equipment of NTT is used, for example.
In the future, with the increase of the amount of information and the development of service functions in the data communication and the expansion of applications of the packet switching operation with respect to new media (such as the image and voice), there will be required a development of a packet switching equipment having a packet switching capacity of about 10.sup.6 packets per second.
However, according to the fundamental constitution of the prior-art packet switching equipment, there is included a multi-processor configuration comprising a uni-bus, a loop bus, and a system of a memory common connection; furthermore, a complicated software processing is achieved through the communications between processors, namely, inter-processor communications and through the communication control protocol processing. Consequently, since an increase in the packet switching traffic immediately causes a contention with respect to the bus and the memory, there has been a disadvantage that when the number of the processors is increased, namely, when the number of the switching modules is increased, the packet switching capacity is lowered.
On the other hand, when the performance of the system is ultimately emphasized and there is adopted as a coupling or linking system for a high-speed transfer a complete coupling or linking system such as a crossbar switch employed in a line switching system, if the number of the basic switching modules is N, there are required N.sup.2 switching elements in the crossbar switch; moreover, in the complete coupling network, it is required to prepare N - 1 input/output ports. This means that the increase in the number N of the modules is disadvantageous with respect to the cost of the system.
Based on the background above, in connection with the processor connecting method for the packet switching equipment coping with the high-speed transfer and the increase of the number of the modules, as described by C. Wu and T. Feng in the "On a Class of Multistage Interconnection Networks", IEEE Trans. Comput., C-29, 8, pp. 694-702 (Aug. 1980), it has been reported to be advantageous to adopt a method including a connecting or coupling system in which the switching modules of the crossbar switch are arranged in a multistage fashion and hence the switch elements are not increased on an order of N.sup.2 like in a case where the single-stage configuration is utilized. This multistage crossbar switch configuration is applicable to a connection of 1000 modules or more, and for example, there exists an example of a multistage switch configuration of an omega network adopted in a super computer of the Burroughs (U.S.) including a multistage connection of shuffle-exchanges.
In the multistage switching network configuration like the omega network above, when an expansion of the network is required, for example, to add subscribers, connections must be established between the additional subscribers and the existing subscribers. Namely, a partial expansion of the network is impossible because the symmetric characteristic of the line connection and the address system of addresses to be assigned to the subscribers cannot be sustained (for example, the hardware transfer cannot be effected only with a destination address), and the alteration of the constitution due to the expansion affects the overall network. In particular, when the network size is increased, the number of connecting lines becomes abruptly great, which hence leads to a problem that the expansion and the configuration change of the network cannot be easily carried out and that in the omega network, if the load imposed on each switch element is not uniform, a fluctuation takes place in the packet data so as to cause a problem of a data loss and a data error and there are required a (flow control) apparatus to control the flow of the packet data and a delay of processing for the pertinent control, which prevents the processing speed from being increased.
Next, description will be given of the prior-art technology of the packet transfer control.
At present, the X.25 Recommendation of CCITT has been widely used as the communication control protocol in the packet switched network. According to the X.25 Recommendation, a call is established through a predetermined connection or link control procedure a call initiation terminal and a call destination terminal until a request to disconnect the call is issued. More concretely, the logical channel is represented by packet identification and control information contained in a header portion of a packet, and the software of the packet switching equipment effects a packet transfer along the logical channel based on the information above. For the hardware of the packet switching equipment, there is commonly adopted a method in which a direct memory access (DMA) transfer is conducted via an internal common bus to a communication line determined by the logical channel.
However, in order to achieve a high-speed packet transfer, it is impossible to employ such a method in which the line connection and the transfer control are effected by the software, namely, these functions must be implemented by the hardware.
A high-speed packet transfer control apparatus utilizing hardware switching elements has been described in the U.S. Pat. No. 3,979,733. In this system, there are included transfer control means determining a route of the next stage or level based on the header portion of a received packet and memory means storing internal information to determine the route such that the transfer timing of the next stage is established in synchronism with a time slot attained through a time-sharing operation.
On the other hand, in a packet transfer control apparatus (bit switch system) employing a network constitution, like the omega network, which includes a multistage connection of switching elements and which is called a bit switch, the time-sharing operation is not achieved to control the transfer timing and hence particular means for the synchronization is not necessary. However, if there exists a fluctuation of the traffic due to the packet transfer at the random timing, the load is concentrated on the bit switch, which leads to the second problem that there may arise a blocking of the acket data at the next stage or level, a data loss, and a data error.